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Ordering number : EN*5155
CMOS LSI
LC82102, LC82102W
Image-Processing LSI for Fax, Copier and OCR Products
Preliminary Overview
The LC82102 and LC82102W convert analog video signals from CCD or contact image sensors to highquality binary video data. The LC82102/W converts the input analog data to multi-valued data and uses twodimensional filtering and an error diffusion technique that produces high-quality images to produce a two-valued image. Finally, the LC82102 reduces the image in the main and subsidiary scan directions. The LC82102 requires absolutely no external memory since it limits the number of pixels processed to 2040 per line. This LSI can implement the image processing used by FAX, copier and OCR products.
Package Dimensions
unit: mm 3159-QFP64E
[LC82102]
Features
* Number of pixels processed: 2040 pixels/line * Processing speed: 500 ns/pixel maximum (when the CLKIN input frequency is 32 MHz) * Built-in 8-bit A/D converter (includes a sensor signal delay adjustment function) * Built-in 6-bit D/A converter for setting the A/D converter high reference potential * Sensor drive circuit (supports CCD and all CIS types) * Digital clamp (single-point clamp, even/odd clamp) * Distortion correction (white correction: 8-pixel averaging correction, black correction: black correction subtraction data setting) * Gamma correction (supports user-defined curves) * Simple binary-conversion processing (fixed threshold level, density-adaptive threshold level) * Intermediate processing error diffusion (64 levels) * Image reduction (thinning, fine black line retaining, fine white line retaining) * Single-voltage 5 V supply and low power due to CMOS process fabrication
SANYO: QIP64E
unit: mm 3190-SQFP64
[LC82102W]
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91195HA (OT) No. 5155-1/5
LC82102, LC82102W
Specifications
Absolute Maximum Ratings at Ta = 25C, GND = 0 V
Parameter Maximum supply voltage Maximum I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions Symbol VDD max VI, VO max Pd max Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 350 -30 to +70 -55 to +125 350 235 Unit V V mW C C C C
Allowable Operating Ranges at Ta = -30 to +70C, GND = 0 V
Parameter Supply voltage Input voltage Symbol VDD VIN Conditions min 4.5 0 typ max 5.5 VDD Unit V V
DC Characteristics at Ta = -30 to +70C, GND = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high level voltage Input low level voltage Input leakage current Output high level voltage Output low level voltage Output leakage current Current drain Symbol VIH VIL IL VOH VOL IL IDD VIN = VDD, VSS IOH = -3 mA IOL = 3 mA For high-impedance output CLKIN = 32 MHz -100 40 -25 2.4 0.4 +100 70 Conditions min 2.2 0.8 +25 typ max Unit V V A V V A mA
Analog Characteristics
Parameter [D/A Converter] Resolution Internal resistance [A/D Converter] when ADREFL = 0 V, and the ATAP potential is 4.2 V Resolution Linearity error Differential linearity error Internal resistance 300 8 1 1 bit LSB LSB 6 5.0 bit k Symbol Conditions min typ max Unit
No. 5155-2/5
LC82102, LC82102W Block Diagram
Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol D7 D6 D5 D4 D3 D2 D1 D0 DGND DVDD A8 A7 A6 A5 A4 A3 DGND A2 A1 A0 I/O B B B B B B B B P P I I I I I I P I I I CPU interface address bus Digital system ground CPU interface address bus A8 is the MSB and A0 is the LSB. Digital system ground Digital system power supply CPU interface data bus D7 is the MSB and D0 is the LSB. Function
Continued on next page. No. 5155-3/5
LC82102, LC82102W
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol WR RD ME DVDD CLKIN TEST IOE MCS IOCS ICLK TRIG RESET SAMP/LININT AP3 AP2 AGND ADREFL DAREFL AIN TEMP ATAP DAREFH AVDD AP1 AP0 AGND PD7/SD PD6/SDCK DGND PD5/SDE PD4/PP4 PD3/PP3 PD2/PP2 PD1/PP1 PD0/PP0 DVDD DACK/PP5 DREQ/PP5 MTP/PP7 CLK2 CLK1 RS SH DGND I/O I I I P I I I I I I I I O O O P I I I I O I P O O P B B P B B B B B B P B B B O O O O P Digital system ground Sensor drive signal output Digital system power supply DMA data acknowledge signal input/general-purpose I/O port DMA data request signal output/general-purpose I/O port Motor drive timing signal output/general-purpose I/O port DMA output/general-purpose I/O ports CPU interface write signal CPU interface read signal CPU interface memory enable signal Digital system power supply System clock input Test pin (Connect to ground in normal use.) CPU interface I/O enable signal CPU interface memory chip select signal CPU interface I/O chip select signal External sampling point signal input External trigger signal input System reset A/D converter sampling point monitor signal output/LINE signal output General-purpose analog ports Digital system ground A/D converter low reference voltage D/A converter low reference voltage Sensor signal input Temperature signal input Intermediate analog connection D/A converter high reference voltage Analog system power supply General-purpose analog ports Analog system ground DMA output/serial data output DMA output/serial data transfer clock Digital system ground DMA output/serial data output valid signal Function
No. 5155-4/5
LC82102, LC82102W Sample Application
1. C1: Use a 0.01 F laminated ceramic capacitor. 2. Set up the polarity of the image signal from the sensor so that white data is represented by the highest potential and black data by the lowest potential. A level conversion circuit can allow the whole dynamic range of the built-in A/D converter to be used effectively if the maximum output level of the peaks in the image signal from the sensor does not reach 4.2 V. 3. Although AGND and DGND are completely isolated internally in this LSI, AVDD and DVDD are connected through the substrate. Therefore, the power supply system must be designed so that no potential difference between AVDD and DVDD can occur. Also, when power is applied or removed, the time lag between the power supplies must be under 3 ms.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. PS No. 5155-5/5

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